1. Field of the Invention
The present invention pertains in a general manner to the field of integrated-circuit electronic systems, called “Systems on a Chip” or SoC.
2. Description of the Related Art
More particularly, the invention relates to the interfacing between functional modules of such a system which comply with the specifications of distinct respective communication protocols.
A functional module of a system on a chip is sometimes called a virtual component or “Intellectual Property” block, or else IP block in the jargon of the person skilled in the art. It is designed to undertake a determined function, or is for general use (it may possibly be a microprocessor or a microcontroller). It can be embodied in the form of hardware elements and/or of software elements.
A distinction is made between modules of master type (hereinafter initiator modules), which take the initiative in exchanging data with one or more other modules, and modules of slave type (hereinafter target modules), whose role is to respond to the requests received from the initiator module which is in charge. Should there be a plurality of initiator modules, an arbitration unit (or arbiter) is responsible for arbitrating in respect of conflicting requests for access to a common resource originating from distinct initiator modules, so as to grant an exclusive right of access to the resource, to a determined one of the said initiator modules.
Conventionally, the functional modules communicate via at least one communication bus comprising a data bus, an address bus and a control bus, complying with the specifications of a determined communication protocol. According to certain protocols the processing of a request may begin with the implementation of a link setup procedure with mutual acknowledgements (otherwise known as “handshake”). The expression link setup procedure is understood to mean a procedure in the course of which the initiator module and the target module exchange control signals, until they are ready for the mutual transmission of data.
When functional modules are designed to comply with the specifications of distinct respective communication protocols, means of interfacing and/or of control are provided so as to allow them to communicate with one another.
Functional modules of initiator type exist, in particular microcontrollers and/or microprocessors, which possess an instruction set comprising composite instructions. The expression composite instruction is understood to mean an instruction which corresponds to more than one elementary operation. In principle, the duration of execution of a composite instruction therefore takes more than one clock cycle of the initiator module.
For example, the instruction set of the ST7 microcontroller from STMicroelectronics possesses a BSET instruction and a BRST instruction, the execution of which takes three cycles of its activation signal (clock signal of the ST7) and which each correspond to several elementary operations for one and the same Operation Code (or “OP Code”). In particular, they implement two requests for access to the target module, of which one is a read request and one a write request. In fact, they correspond in total to three elementary operations or atomic level operations, that is to say of lower protocol level, which is the level of an operation of the microcode corresponding to a request.
The interfacing of an initiator module thus having an instruction set comprising at least one composite instruction with a determined target module, which is performed when the two functional modules comply with different communication protocols, may then pose specific problems.
In particular, if the target module provides for the execution of a “handshake” before processing each request, provision must be made for an interface and control module to implement a particular processing during the execution of a composite instruction, which module effects the interface between the initiator module and the target module. Specifically, given that, from the point of view of the target module, there are several successive and distinct access requests (two in the example of the BSET and BRST composite instructions of the ST7 microcontroller), it is necessary to perform a “handshake” for the execution of each of the said requests, although they correspond to the processing of just a single instruction.
Furthermore, when an arbitration mechanism is provided to arbitrate in respect of conflicting requests originating from several distinct initiator modules, it may be necessary to provide measures to avoid another initiator module being able to obtain the right of access during the execution of the successive requests corresponding to one and the same instruction executed by a determined initiator module.
Now, certain at least of the known initiator modules, and in particular the aforesaid ST7 microcontroller, do not output information indicating directly whether the instruction undergoing execution is or is not a composite instruction. Such information may be rendered available inside the initiator module, in particular at the instruction decoding level, but it is not accessible from outside and is therefore not utilizable for the interfacing.
It follows that the interfacing of such a functional module with other functional modules complying with the specifications of a different communication protocol poses a problem of a protocol nature, which does not come within the conventional framework of the shaping of signals at the electrical level.